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integrated circuit systems, inc. ics9250-22 third party brands and names are the property of their respective owners. 9250-22 rev b 12/08/00 pin configuration 56-pin 300mil ssop & tssop recommended application: p iv chipset support output features: ? 4 differential cpu clock pairs @ 3.3v 2 - 3v mref clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) 4 - 66mhz reference output 10 - 3v 33mhz pci clocks 2 - 48mhz clocks 2 - 14.318 reference output features: support power management: power down mode supports spread spectrum modulation: 0 to -0.5% down spread. uses external 14.318mhz crystal select logic for differential swing control, test mode, tristate, power down, spread spectrum, limited frequency select, selective clock enable. external resistor for current reference fs pins for frequency select key specifications: ? 3v66 output jitter <300ps cpu output jitter <200ps mref output jitter <250ps frequency generator for p iv? gnd ref vddref x1 x2 gndref pciclk0 pciclk1 vddpci pciclk2 pciclk3 gndpci pciclk4 pciclk5 vddpci pciclk6 pciclk7 gndpci pciclk8 pciclk9 vddpci sel100/133 gnd48 48mhz 48mhz vdd48 pd# multsel0/ multsel1/ref fs0/ fs1/ vddmref 3vmref 3vmref_b gndmref spread# cpuclkst3 cpuclksc3 vddcpu cpuclkst2 cpuclksc2 gndcpu cpuclkst1 cpuclksc1 vddcpu cpuclkst0 cpuclksc0 gndcpu i ref vdda gnda vdd3v66 3v66-3 3v66-2 gnd3v66 gnd3v66 3v66-1 3v66-0 vdd3v66 ics9250-22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 functionality pll2 pll1 spread spectrum 48mhz 3vmref pciclk (9:0) 3vmref_b 3v66 (3:0) 4 10 2 2 x1 x2 xtal osc cpu divder 3vmref divder pci divder 3v66 divder pd# spread# multsel (1:0) sel100/133 fs(1:0) control logic config. reg. ref 4 4 cpuclkst (3:0) cpuclksc (3:0) / 3 3 1 l e s 0 0 1 0 s f1 s fn o i t c n u f 000 z h m 0 0 1 e v i t c a 001 ) d e v r e s e r ( 010 ) d e v r e s e r ( 011 s t u p t u o l l a e t a t s i r t 100 z h m 3 3 1 e v i t c a 101 ) d e v r e s e r ( 110 ) d e v r e s e r ( 111 e d o m t s e t block diagram power groups vddref, gndref= ref, x1, x2 vddpci, gndpci = pciclk vdd48, gnd48 = 48mhz, pll2 vdd3v66, gnd3v66=3v66 vddcpu, gndcpu = cpuclk vddmref, gndmref=3vmref, 3vmref_b vdda=vdd (core supply voltage 3.3v) gnda=ground for core supply ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9250-22 third party brands and names are the property of their respective owners. general description pin configuration the ics9250-22 is a single chip clock solution. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-22 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 2 3 , 4 2 , 9 1 , 3 1 , 7 , 1 3 5 , 6 4 , 0 4 , 7 3 , 3 3 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 2 , 3) 0 : 1 ( l e s t l u m / f e rn i d n a p u - r e w o p n o d e s n e s e r a s t u p n i 1 l e s t l u m d n a 0 l e s t l u m v 3 n o t u p t u o r o f d e s u g n i e b n i p e h t o t r o i r p d e h c t a l y l l a n r e t n i n e h t . s k c o l c z h m 8 1 3 . 4 1 , 9 2 , 7 2 , 2 2 , 6 1 , 0 1 , 4 6 5 , 9 4 , 3 4 , 8 3 , 6 3 d d vr w py l p p u s r e w o p v 3 . 3 51 xt u p n i l a t s y r c 2 xt u p n i l a t s y r c z h m 8 1 3 . 4 1 62 xt u p t u o l a t s y r c 1 xt u p t u o l a t s y r c z h m 8 1 3 . 4 1 , 5 1 , 7 1 , 8 1 , 0 2 , 1 2 8 , 9 , 1 1 , 2 1 , 4 1 ) 0 : 9 ( k l c i c pt u os t u p t u o k c o l c i c p 3 23 3 1 / 0 0 1 l e sn iz h m 3 3 1 = h g i h , z h m 0 0 1 = w o l . t c e l e s y c n e u q e r f u p c 5 2 , 6 2 ) 0 : 1 ( s fn is n i p t c e l e s y c n e u q e r f z h m 8 4t u ot u p t u o k c o l c z h m 8 4 8 2# d pn i. w o l e v i t c a . e d o m n w o d - r e w o p s e k o v n i 0 3 , 1 3 , 4 3 , 5 3) 0 : 3 ( 6 6 v 3t u os k c o l c e c n e r e f e r z h m 6 6 9 3f e r it u o . s r i a p k l c u p c e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i l b a t s e n i p s i h t o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s i c e r p d e x i f a s e k a t n i p s i h t . t n e r r u c e t a i r p o r p p a e h t h s i l b a t s e 2 4 , 5 4 , 8 4 , 1 5) 0 : 3 ( t s k l c u p ct u o d e h c t i w s e r a e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " e u r t " . s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o t n e r r u c 1 4 , 4 4 , 7 4 , 0 5) 0 : 3 ( c s k l c u p ct u o e s e h t . s t u p t u o u p c r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a s t u p t u o t n e r r u c d e h c t i w s e r a . s a i b e g a t l o v 2 5# d a e r p sn i t s o h l a i t n e r e f f i d e h t n o y t i l a n o i t c n u f m u r t c e p s d a e r p s s e k o v n i i c p z h m 3 3 d n a , s k c o l c z h m 6 6 , s k c o l c b _ f e r m / f e r m , s k c o l c w o l e v i t c a . s k c o l c 4 5b _ f e r m v 3t u o r e v i r d k c o l c y r o m e m o t e c n e r e f e r v 3 ) f e r m v 3 h t i w e s a h p f o t u o ( 5 5f e r m v 3t u or e v i r d k c o l c y r o m e m o t e c n e r e f e r v 3
3 ics9250-22 third party brands and names are the property of their respective owners. truth table group offset limits p u o r gt e s f f o s d a o l t n e m e r u s a e m ) d e p m u l ( s t n i o p e r u s a e m 6 6 v 3 o t u p ct n e m e r i u q e r o n i c p o t u p c i c p o t 6 6 v 3 s n 5 . 3 - 5 . 1 s d a e l 6 6 v 3 f p 0 3v 5 . 1 l e s 0 0 1 / 3 3 1 0 s f1 s fu p cf e r m6 6 v 3i c pz h m 8 4f e r 000 z h m 0 0 1z h m 0 5z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1 001a / na / na / na / na / na / n 010a / na / na / na / na / na / n 011 e t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r te t a t s i r t 100 z h m 3 3 1z h m 6 6z h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1 101a / na / na / na / na / na / n 110a / na / na / na / na / na / n 111 2 / k l c t4 / k l c tk l c t6 / k l c tk l c t
4 ics9250-22 third party brands and names are the property of their respective owners. cpuclk buffer configuration s n o i t i d n o cn o i t a r u g i f n o cd a o ln i mx a m t u o i ) v 0 3 . 3 ( l a n i m o n = d d v , 0 m f o s n o i t a n i b m o c l l a n i n w o h s r r d n a 1 m w o l e b e l b a t r o f d a o l t s e t l a n i m o n n o i t a r u g i f n o c n e v i g % 7 - i l a n i m o n% 7 + i l a n i m o n t u o i % 5 0 3 . 3 = d d v , 0 m f o s n o i t a n i b m o c l l a n i n w o h s r r d n a 1 m w o l e b e l b a t r o f d a o l t s e t l a n i m o n n o i t a r u g i f n o c n e v i g % 2 1 - i l a n i m o n% 2 1 + i l a n i m o n 0 l e s t l u m1 l e s t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i ) r r * 3 ( / d d v t u p t u o t n e r r u c , z @ h o v a m 2 3 . 2 = f e r i 00 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 6 @ v 1 7 . 0 00 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 5 @ v 9 5 . 0 01 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 6 2 / v 5 8 . 0 01 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 1 7 . 0 10 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 6 @ v 6 5 . 0 10 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 5 @ v 7 4 . 0 11 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 6 @ v 9 9 . 0 11 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 5 @ v 2 8 . 0 00 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 3 @ v 5 7 . 0 00 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 2 @ v 2 6 . 0 01 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 3 @ v 0 9 . 0 01 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 2 @ v 5 7 . 0 10 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ 0 6 . 0 10 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ v 5 . 0 11 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 3 @ v 5 0 . 1 11 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 2 @ v 4 8 . 0 cpuclk swing select functions
5 ics9250-22 third party brands and names are the property of their respective owners. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a i il1 v in = 0 v; inputs with no pull-up resistors -5 a i il2 v in = 0 v; inputs with pull-up resistors -200 operating supply current i dd3.3op c l = 0 pf; select @ 100 mhz 130 250 ma powerdown current i dd3.3pd c l = 0 pf; input address to vdd or gnd 35 60 ma input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l p i n 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3 ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. delay 1 input capacitance 1 input low current
6 ics9250-22 third party brands and names are the property of their respective owners. electrical characteristics - cpu t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 714 ? output impedance r dsn2b 1 v o = v dd *(0.5) 714 ? output high voltage v oh2b i oh = -1 ma 2 v output low voltage v ol2b i ol = 1 ma 0.4 v output high current i oh2b 2 v oh @ min = 1.0 v, v oh @ max = 2.375 v -27 -27 ma output low current i ol2b 2 v ol @ min = 1.2 v, v ol @ max = 0.3 v 27 30 ma rise time t r2b 1 v ol = 20%, v oh = 80% 175 500 700 ps fall time t f2b 1 v oh = 80%, v ol = 20% 175 500 700 ps duty cycle d t2b 1 v t = 50% 45 51 55 % skew t sk2b 1 v t = 50% 110 150 ps jitter t jcyc-cyc 1 v t = 50% 110 200 ps 1 guaranteed by design, not 100% tested in production. 2 i owt can be varied and is selectable thru the multsel pin. electrical characteristics - pci t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @ max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.4 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.4 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 270 500 ps jitter t jcyc-cyc 1 v t = 1.5 v 115 500 ps 1 guaranteed by design, not 100% tested in production.
7 ics9250-22 third party brands and names are the property of their respective owners. electrical characteristics - mref/mref_b t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @ max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.4 1.6 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.4 1.6 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 80 100 ps jitter t jcyc-cyc 1 v t = 1.5 v 105 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -29 -23 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @ max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 124ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 124ns duty cycle d t1 1 v t = 1.5 v 45 50 55 % skew t sk1 1 v t = 1.5 v n/a ps jitter t jcyc-cyc 1 v t = 1.5 v 205 1000 ps 1 guaranteed by design, not 100% tested in production.
8 ics9250-22 third party brands and names are the property of their respective owners. electrical characteristics - 48mhz t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 48 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -29 -23 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @ max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 124ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 124ns duty cycle d t1 1 v t = 1.5 v 45 54 55 % skew t sk1 1 v t = 1.5 v n/a ps jitter t jcyc-cyc 1 v t = 1.5 v 120 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 3v66 t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 33 55 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.55 v output high current i oh 1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol 1 v ol @ min = 1.95 v, v ol @ max = 0.4 v 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.3 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.3 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 85 250 ps jitter t jcyc-cyc 1 v t = 1.5 v 80 300 ps 1 guaranteed by design, not 100% tested in production.
9 ics9250-22 third party brands and names are the property of their respective owners. pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. notes: 1. as shown, the outputs stop low on the next falling edge after pd# goes low. 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 3. the shaded sections on the vco and the crystal signals indicate an active clock. mref mref_bar cpuclkt cpuclkc vco crystal pd#
10 ics9250-22 third party brands and names are the property of their respective owners. ordering information ics9250 y f-22-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations
11 ics9250-22 third party brands and names are the property of their respective owners. ordering information ics9250 y g-22-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type g=tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp - t ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (0.020 mil) min max min max a - 1.20 - .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e 0.50 basic 0.020 basic l 0.45 0.75 .018 .30 n 0 8 0 8 aaa - 0.10 - .004 variations min max min max 56 13.90 14.10 .547 .555 mo-153 jedec doc.# 10-0039 7/6/00 rev b symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations 8.10 basic 0.319 n d mm. d (inch) see variations

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